RSA Encryption and Decryption Implementation in an FPGA Using Verilog HDL
Authors:
Dr. Mohammad H. Awedh 1, Dr. Ahmed Mueen 2
Associate Professor, Department of Electrical and Computer Engineering, Faculty of Engineering, King Abdulaziz University, Saudi Arabia
1
Associate Professor, Department of Computer and Information Technology, King Abdulaziz University, Saudi Arabia
2
doi.org/10.52132/Ajrsp.e.2025.74.2
The main objective of this project is to create a hardware-based system that is capable of encrypting plaintext and decrypting ciphertext when the public or private key and modulus n are given. Normally, the RSA algorithm has performance limitations in software-based realizations due to its computational difficulty in prime factorization. Our proposed design addresses this issue by utilizing the parallel processing capabilities of FPGA architectures. For efficient cryptographic processing, we have developed and optimized components such as modular multiplication and modular exponentiation using Verilog HDL. The results show that FPGA-based implementations are more suitable for secure real-time and embedded cryptographic applications as compared to traditional software approaches. Based on the result of this research the authors recommend to focus on optimizing cryptographic hardware for power efficiency and scalability, especially for use in IoT and edge devices, and encouraged to explore the integration of RSA hardware modules with other security protocols for comprehensive system-on-chip (SoC) solutions, also recommend the educational institutions and training programs to incorporate practical FPGA-based cryptographic projects to bridge the gap between theory and application and continuing to refine RSA hardware implementations and exploring new architectural strategies.
Keywords:
Cryptography, RSA algorithm, FPGA architecture, Real-time and Embedded cryptographic, Hardware Description Language, UART.