An FPGA Implementation of the SHAKE256 Cryptographic Hash Function Based on the Keccak-f[1600] Permutation
Authors:
Dr. Mohammad H. Awedh
Associate Professor, Department of Electrical and Computer Engineering, Faculty of Engineering, King Abdulaziz University, Saudi Arabia
doi.org/10.52132/Ajrsp.e.2026.83.1
This paper presents an area-efficient hardware implementation of the SHAKE256 cryptographic hash function based on the Keccak-f[1600] permutation, targeting resource-constrained FPGA platforms. The proposed design employs a modular Verilog HDL architecture centered on a single permutation core controlled by finite state machines, prioritizing logic reuse, architectural clarity, and full standards compliance over aggressive pipelining. Unlike high-throughput architectures that rely on extensive parallelism and large silicon footprints, this implementation emphasizes balanced trade-offs between performance, area, power consumption, and design transparency. The design fully complies with the SHA-3 specification defined in FIPS 202 and supports fixed-length SHAKE256 output generation. The complete system is synthesized and implemented on an Altera Cyclone II FPGA and validated using official NIST test vectors. Experimental results confirm correct functionality, moderate resource utilization, and competitive area efficiency, demonstrating that SHAKE256 can be reliably deployed on low-cost FPGA platforms for cryptographic prototyping, education, and embedded security applications. Based on the obtained implementation results, the author recommends the adoption of modular and area-efficient architectures for SHA-3 and SHAKE-based cryptographic primitives when targeting resource-constrained FPGA platforms. The presented design demonstrates that a balanced approach emphasizing logic reuse, deterministic control, and architectural clarity can achieve reliable cryptographic functionality without requiring extensive hardware resources or aggressive pipelining.
Keywords:
SHAKE256, SHA-3, Keccak-f[1600], FPGA implementation, area-efficient hardware, finite state machine, cryptographic hash functions, hardware security
Academic Journal of Research and Scientific Publishing
